The present disclosure relates to computer-implemented methods, computer program products and computer systems that reduce a number of circuit simulations for a timing analysis of a digital integrated circuit (IC), which comprises multiple cells. In particular, timing constraints from liberty files provide a range of input data slews and a range of output reference slews, which include pushout, for the timing arcs of the digital IC. More particularly, a sequence of analyses, each including an input data slew and an output reference slew, is organized as a matrix for the timing analysis of each timing arc of the digital IC.
During design, timing analysis constitutes a majority of the characterization of a digital integrated circuit (IC) comprising multiple cells. A timing analysis can include a setup time constraint (tSu) or a hold time constraint (tH) for each timing arc of the digital IC. FIGS. 1(a) and 1(b) illustrate a timing analysis of, for example, setup time constraints, tSu 140 for the cell 150 of FIG. 1(c). Clock, Clk(t) 110, and data, D(t) 120, signals drive the cell 150. The result is an output transition, Q(t) 130, where V(out) changes from low to high; typically, the time value of Q(t) 130 is measured at 50% of V(out). Timing constraint analysis generally “fixes” the clock signal, Clk(t) 110, while varying the input data signal, D(t) 120, to obtain the resultant output transition, Q(t) 130. The following relationship between the clock signal, Clk(t) 110, the data signal, D(t) 120, and the setup time, tSu 140, must be true for the output transition, Q(t) 130, to occur: Clk(t)>(D(t)+tSu), i.e., the setup time, tSu 140, is the minimum amount of time by which the input data signal, D(t) 120, must precede the clock signal, Clk(t) 110, in order to cause the output transition, Q(t) 130.
FIG. 1(a) illustrates that relative to the fixed time value of the clock signal, a large setup time, tSu, is associated with a data signal, D(t), having a small time value, i.e., to the left on the time axis, while a small setup time, tSu, is associated with a data signal, D(t), having a large time value, i.e., to the right on the time axis. FIG. 1(a) also illustrates that smaller setup times, i.e., later data transitions, are associated with output transitions of Q(t), which are characterized by a greater time values at their 50% amplitudes, the so-called “pushout”.
Characterization, or violation analysis, determines the setup time, tSu 140, of the cell. To determine the setup time, tSu 140, of the cell 150, a circuit simulator keeps the Clk(t) 110 waveform fixed, while repeating circuit simulations with the different D(t) 120 waveforms. The circuit simulator then observes which D(t) 120 waveforms produce an output transition, Q(t) 130, and which do not. A linear search method can be used that requires a tight sweep of delays between the data setup and the clock edge, which looks for a minimal setup time at which the output transition just occurs, and is accurate only if the sweep step is very small, which requires a very large number of steps.
To avoid the very large number of circuit simulations in a linear search method, a binary search is used to measure a timing constraint of a cell. A binary search is an optimization method that finds a target value of an input variable, e.g., a data setup time before the fixed clock or a data hold time after the fixed clock, which is associated with a goal value of an output variable, e.g., a V(out), for the cell indicating a transition from low to high. The input and output variables can be any of a voltage, a current, a setup time, a hold time, or a gain that are related by a transfer function associated with the circuit simulation.
A binary search is used to locate the target value of the input variable that just produces the output goal value within a search range of the input variable. The search range is iteratively halved or bisected to converge on the target value of the input variable. At each of the iterations, the timing analyzer of the circuit simulator compares the measured value of the output variable with the goal value. A bisection method involves both measurement and optimization steps when solving a timing violation problem: 1) detecting whether the measured goal value of the output variable has occurred, e.g., the V(out) for Q(t); and 2) optimizing a search range for the input parameter, e.g., data setup time, tSu, to find the target value for which the measured goal value of the output transition just occurs.
Referring to FIG. 2(a), the bisection method requires a search window comprising an upper boundary XU, 190 and a lower boundary XL, 160 to be specified for the input variable, X. To begin the bisection method in the case of a data setup time, tSu, a simulation of the upper boundary XU, 190 must result in the output variable yielding a “pass”, i.e., Y (VOUT) of Q(t) being equal to or greater than (or to the right of) the output variable's goal value, 175, which is associated with the desired target value; while a simulation of the lower boundary XL, 160 must result in the output variable yielding a “fail”, i.e., Y (VOUT) of Q(t) being less than (or to the left of) the goal value, 175. Having simulated a sequential “pass” and “fail”, the bisection method then simulates an input variable located halfway between the upper boundary XU, 190 and the lower boundary XL, 160, i.e., the first bisection point X1, 180, which equals (XU+XL)/2. If the simulation of the first bisection point X1 passes, then the target value of the input variable X must be less than that of the first bisection point X1. As indicated in FIG. 2(b), the bisection method then moves the upper boundary, XU, of the input variable to the first bisection point X1, which passed the simulation, as the new upper boundary of a new search window. If the simulation of the first bisection point X1 were to fail, then the target value of the input variable X must have been greater than that of the first bisection point X1, and the method would then have moved the lower boundary to the first bisection point X1, as the new lower boundary.
Referring to FIG. 2(b), after establishing a new upper boundary at the first bisection point X1, the bisection method then iteratively simulates the input variable located midway between new upper boundary at the first bisection point, X1, and the lower boundary, XL, i.e., the second bisection point X2, 170, which equals (X1+XL)/2. If, as is the case in FIG. 2(b), the simulation of the second bisection point X2 fails, then the target value of the input variable X must be greater than that of the second bisection point, X2. As indicated in FIG. 2(c), the bisection method then moves the lower boundary, XL, to the second bisection point, X2, which failed the simulation, as the new lower boundary for the next search window. The method will then iteratively simulate the input variable located midway between the new upper boundary at the first bisection point, X1, and the new lower boundary at the second bisection point, X2, at the third bisection point, X3, which equals (X1+X2)/2.
The binary search continues in the manner described above, moving either the upper boundary or the lower boundary to the last simulated bisection point, and iteratively simulating a new bisection point between new boundaries to form new search windows. The iterations of the bisection method stop, when a difference between the last simulated value of the last bisection point and the newly simulated value of the new bisection point is less than or equal to a specified error tolerance. A conventional binary method can require several tens of iterations to converge, making the cost of simulation high.
A conventional characterization of a digital IC includes not only a range of input data timing variables applied to each cell and a fixed output transition to determine, for example, a setup time, tSu, but also data related to each voltage threshold of each cell type, each process variation, each set of operating conditions for each cell, and each timing arc.
Conventional characterization of the output transition, using a binary search, does not take into account, the various time values of the “pushout” of output transitions, which vary not only with smaller setup time values but also with cell type. Thus, the conventional timing tools are forced to extrapolate timing values for the desired data/reference signal slew ranges, which negatively affects accuracy, adds pessimism, and affects yields.
There remains a need to analyze a timing constraint of a digital IC that takes advantage of the efficiencies of a binary search and provides an accurate timing analysis for each of the timing arcs, which are characterized by various time values of the “pushout” of output transitions.